One big problem is that formal verification is still so new to mainstream usage that there are many players, all of whom are happily charging around in a bewildering variety of different directions. Having said this, formal verification can be such an incredibly powerful tool that more and more folks are starting to use it in earnest. This is particularly true in the FPGA arena, where the adoption of formal verification is lagging behind its use in ASIC design flows. Although large computer and chip companies like IBM, Intel, and Motorola have been developing and using formal tools internally for decades (since around the mid-1980s), the whole field of formal verification (FV) is still relatively new to a lot of folks.
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